An At Speed Structural Test (ASST) capability to application-specific integrated circuit (ASIC) offerings is disclosed in copending U.S. patent application Ser. No. 10/906,407, the disclosure of which is expressly incorporated by reference herein in its entirety. The ASST test structures described here are programmable and test clock domain by clock domain. These structures are programmable through scan chains and provide a chip fully constrained for manufacturing test. A fully constrained design is one where control of the on board clock generation circuits (PLLs and clock formatters) are under scan programming control for manufacturing test. In order to perform these tests, design for test (DFT) logic was added to the chip design in a manner which facilitates the inclusion of an At Speed LBIST described in this patent. These controls are slow (not at functional speeds) and the logic in copending U.S. patent application Ser. No. 10/906,407 causes the at speed clock responses to occur.
The state of the art today is for a custom LBIST to be designed for each chip design. This custom LBIST design is very labor insensitive, time consuming and requires an intimate knowledge of the design and engineering expertise. Each design is unique and not reusable.
The ASST approach described in U.S. patent application Ser. No. 10/906,407 is a DFT process which results in a fully constrained chip in which the phase locked loop (PLL) operation, turning clocks off and on, setting up clock trees for test are under test control through programming bits. The programming necessary for ASST testing is determined from the manufacturing test for the specific chip, and the testing is accomplished by loading scan bits in the design. This ASST structure can then be coupled with a microcontroller which can be supplied with scan bits determined during manufacturing test generation to deliver a LBIST solution.